杰发科技AC7803——不同晶振频率时钟的配置

计算公式

PLL_POSDIV       [2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62]
PLL_PREDIV_1     1 2 4
USE_XTAL       = 24M   
SYSCLK_FREQ    = 64M
SYSCLK_DIVIDER = 1
VCO            = USE_XTAL* FBKDIV / PREDIV     24*FBKDIV/2
SYSCLK_FREQ    = VCO / POSDIV / SYSCLK_DIV     64 = 24*FBKDIV/2/ （2-62)/1   PREDIV = 2， SYSCLK_DIV = 1，POSDIV = 12，
24*FBKDIV/2
64 = 24*FBKDIV/2/12/1   
64*1*12*2=24*FBKDIV
FBKDIV = 64

 修改为24M晶振，可以参考12M晶振配置

	#define HSI_FREQ      8000000UL   /*!< Internal 8M RC clock */#define XTAL_8M       8000000UL   /*!< extern crystal oscillator 8M  */#define XTAL_12M     12000000UL   /*!< extern crystal oscillator 12M */#define XTAL_16M     16000000UL   /*!< extern crystal oscillator 16M */#define XTAL_30M     30000000UL   /*!< extern crystal oscillator 30M */#define XTAL_24M     24000000UL   /*!< extern crystal oscillator 30M */#define USE_XTAL     XTAL_24M      /*!< Select the actual crystal frequency */#define CKGEN_AUTO_CHANGE_CLK  1U  /*!< Auto change system clock to internal clock after detect xosc or pll fail *//*!< PLL configure */#ifndef PLL_CONFIG_72M  /* Output 64MHz */#if USE_XTAL == XTAL_8M#define PLL_POSDIV   PLL_POSDIV_8#define PLL_FBKDIV   64U#define PLL_PREDIV   PLL_PREDIV_1#elif USE_XTAL == XTAL_12M#define PLL_POSDIV   PLL_POSDIV_12#define PLL_FBKDIV   64U#define PLL_PREDIV   PLL_PREDIV_1#elif USE_XTAL == XTAL_16M#define PLL_POSDIV   PLL_POSDIV_8#define PLL_FBKDIV   64U#define PLL_PREDIV   PLL_PREDIV_2#elif USE_XTAL == XTAL_30M  /* Output 64MHz */#define PLL_POSDIV   PLL_POSDIV_20#define PLL_FBKDIV   160U#define PLL_PREDIV   PLL_PREDIV_4#elif USE_XTAL == XTAL_24M  /* Output 64MHz */#define PLL_POSDIV   PLL_POSDIV_12#define PLL_FBKDIV   64U#define PLL_PREDIV   PLL_PREDIV_2